Marvell Structera X 3406 and 3506 Bring Six-Channel CXL Memory to AI Inference Racks

As of 20 October 2026, Marvell’s Structera X 3406 and Structera X 3506 are newly announced second-generation CXL memory-expansion controllers, not broadly available parts. Marvell announced the controllers on 12 October 2026 and says they are expected to sample in Q1 2027. The timing matters because AI inference systems are increasingly limited not only by accelerator count, but by how much memory can be placed near CPUs and XPUs without wasting capacity across individual servers. Structera X is aimed at that gap: it uses CXL 3.2 over PCIe 6.0 to attach large banks of DDR memory to hosts, giving rack designers another way to scale memory capacity for workloads such as LLM serving, long-context inference, and recommendation models. (investor.marvell.com)

The most important change versus Marvell’s earlier Structera X 2404 and 2504 generation is the move from four memory channels to six memory channels. ServeTheHome highlighted this as a notable step because it places 50% more channels behind one controller, with the 3406 serving DDR4 designs and the 3506 serving DDR5 designs. Marvell lists the following key configuration details:

Modern inference racks often focus attention on GPUs or other accelerators, but the surrounding memory system can be just as critical. Larger models, longer context windows, and KV-cache growth can all push beyond what is efficient to keep only in local accelerator memory. CXL memory expansion does not replace high-bandwidth memory on an accelerator; instead, it creates another tier of attached system memory that can help hosts feed inference workloads with more capacity. For data-center teams, that can be especially relevant when a model-serving cluster needs to hold more context, larger embedding tables, or more concurrent sessions without redesigning every node around maximum local DRAM. Marvell positions Structera X 3406 and 3506 for this memory-bound side of AI infrastructure, with the DDR4 version also giving operators a possible path to reuse large DDR4 RDIMM pools in newer CXL-capable systems. (investor.marvell.com)

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Structera X 3406 and 3506 also include inline LZ4 compression, with Marvell listing up to 250GB/s compression and decompression throughput. For unreleased hardware, that figure should be read as a vendor specification rather than an independently tested result. The controllers also include StructGuard RAS features for memory reliability, along with Caliptra 2.0, CXL IDE, AES-256 memory encryption, and post-quantum cryptography support. Those details may sound deep in the weeds, but they matter in shared-memory environments: once memory is pooled across hosts, infrastructure teams have to think harder about isolation, data protection, and fault handling, not just raw capacity. (investor.marvell.com)

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The Structera X 3406 and 3506 announcement is less about a single add-in card and more about where AI server design is heading. If Q1 2027 sampling stays on track, the next questions will be platform support, firmware maturity, operating-system integration, and how OEMs package CXL-attached memory inside real inference racks. The headline is clear enough: memory expansion is becoming a first-class part of AI infrastructure planning. GPUs and accelerators still do the heavy compute work, but CXL controllers such as Structera X 3406 and 3506 are pushing the industry toward racks where memory can be scaled, shared, and managed with more flexibility than traditional per-server DRAM layouts.

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