Microchip PIC64-HPSC Brings 64-bit RISC-V Closer to Next-Gen Spaceflight Computing

As of October 29, 2026, Microchip’s PIC64-HPSC High-Performance Spaceflight Computing Series has taken a more concrete step toward real mission use. On October 27, 2026, Microchip announced new program milestones for the platform, positioning it as a 64-bit multicore RISC-V computing family for spacecraft, satellites, and other mission-critical space systems. The update matters because space computing has been stuck between two difficult needs: systems must be resilient enough for radiation-heavy environments, but also powerful enough for data-intensive spacecraft that do more onboard instead of waiting for Earth-based commands. (ir.microchip.com)

The headline technical update centers on the PIC64-HPSC1000-RH, the radiation-hardened variant of the family. Microchip says early radiation characterization demonstrated 200 krad(Si) Total Ionizing Dose performance and successful Single Event Latch-up testing to 78.2 MeV·cm²/mg under specified operating conditions. The company also reported robust system-controller operation during completed Single Event Effects characterization, with no uncorrected errors or external resets required in the testing completed to date. These figures do not make the chip a finished spacecraft computer by themselves, but they give aerospace teams more practical data to weigh as they design platforms for low Earth orbit, lunar, Mars, and deeper-space mission profiles. (ir.microchip.com)

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Microchip lists the PIC64-HPSC series as a family of 64-bit radiation-hardened and radiation-tolerant MPUs. The product page describes the compute side as using ten 64-bit SiFive RISC-V cores, with support for Symmetric Multiprocessing, Asymmetric Multiprocessing, real-time determinism, and virtualization. The feature set also includes vector processing, AI/ML processing support, secure boot, application crypto acceleration, post-quantum cryptography, Ethernet and TSN switching, SpaceWire, PCIe Gen 3, and CXL 2.0. Microchip separates the family into variants such as the PIC64-HPSC1000 Radiation-Hardened MPU, aimed at MEO, GEO, and deep-space profiles, and the PIC64-HPSC1100 Radiation-Tolerant MPU, aimed more at LEO and New Space applications. (microchip.com)

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NASA’s High Performance Spaceflight Computing project gives the broader context. The agency says HPSC is intended to address the computational performance, power management, fault tolerance, and connectivity needs of NASA missions through 2040 and beyond. The project is also built around an industry-standard, open-source instruction set architecture, paired with radiation tolerance, fault tolerance, security, software support, and modern interfaces. In practical terms, that points to spacecraft that can process more sensor data onboard, run autonomous decision-making workloads, handle image and signal processing, and reduce dependence on constant ground intervention when distance or bandwidth gets in the way. (nasa.gov)

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Microchip says select customers are already evaluating silicon and development kits through the PIC64-HPSC Early Access Program, with access to development platforms, software, tools, technical resources, and engineering support. The company also says board partners are working on VPX and VNX+ computing platforms based on PIC64-HPSC, which could give spacecraft developers more integration routes than a chip-only approach. Microchip’s evaluation platform is described as modular, with Peripheral Daughter Cards, NVRAM card options, an optional expansion kit, a Board Support Package, boot firmware, Linux and RTEMS support, and Debian Linux pre-installed on the evaluation platform. (ir.microchip.com)

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The PIC64-HPSC is not being framed as a consumer-style processor launch, and Microchip has not presented it as a finished mass-market computing product. Instead, its current importance is that it is moving into the hands of early aerospace evaluators with measurable radiation data, operational silicon, and a growing board ecosystem. For mission designers, the appeal is not simply having more compute in space; it is having compute that can support autonomy, communications, payload processing, spacecraft control, and secure operations while still being built for harsh environments. That makes the latest milestone a notable point in the shift from older, highly constrained flight computers toward more capable onboard platforms for the next generation of spacecraft. (ir.microchip.com)

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