TSMC’s CoPoS Path Highlights Why CoWoS Remains Key for Huge AI Packages

As of June 27, 2026, TSMC’s latest advanced-packaging discussion has made one thing clear: the next wave of AI processors will not be defined only by smaller transistors. The way multiple pieces of silicon are connected inside one package is now just as important. Tom’s Hardware reported on June 16, 2026, from TSMC’s European Technology Symposium, that panel-level packaging is being explored for far larger chip packages, but TSMC does not see it replacing wafer-level CoWoS for the largest AI processors anytime soon. That matters because modern AI accelerators need huge amounts of compute silicon placed very close to high-bandwidth memory, and that is exactly where advanced packaging becomes a strategic technology rather than a background manufacturing step. (tomshardware.com)

CoWoS, short for Chip-on-Wafer-on-Substrate, is TSMC’s established packaging family for high-performance computing and AI. TSMC’s own 3DFabric documentation describes CoWoS-S as a wafer-level system-integration technology using a large silicon interposer to connect logic chiplets and HBM stacks with dense interconnects. CoWoS-R and CoWoS-L extend the idea with redistribution-layer and local-silicon-interconnect approaches, giving chip designers more options when packages grow beyond certain interposer sizes. In practical terms, CoWoS is valuable because it helps move data quickly between compute dies and memory, which is a core requirement for training and serving large AI models. (3dfabric.tsmc.com)

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CoPoS, or Chip-on-Panel-on-Substrate, is interesting because panel-level manufacturing can potentially provide a much larger physical working area than circular wafers. Tom’s Hardware noted that current large CoWoS substrates are discussed around 120mm × 150mm, next-generation CoWoS can move toward 150mm × 250mm, while early panel concepts can start around 310mm × 310mm and future panels may grow larger. That sounds like an obvious win, but package area is only one side of the tradeoff. TSMC’s message was more cautious: panel-level tools and processes are not yet at the same maturity or interconnect capability as wafer-level methods. Bigger panels may help with cost and scale later, but for the biggest AI chips, dense and reliable wiring still carries enormous weight. (tomshardware.com)

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TSMC is not treating CoWoS as a dead-end bridge to panel packaging. At its 2026 North America Technology Symposium, the company said it was already producing 5.5-reticle-size CoWoS and planning larger versions. A 14-reticle-size CoWoS option is slated for production in 2028 and is described as capable of integrating approximately 10 large compute dies and 20 HBM stacks. TSMC also said this would be followed by an expansion beyond 14 reticles in 2029, alongside a 40-reticle-size SoW-X System-on-Wafer technology expected in 2029. That roadmap explains why CoPoS is better understood as an additional path rather than an instant replacement. (pr.tsmc.com)

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For readers familiar with GPUs, the simple way to view this is that the package is becoming a mini system board, but built with semiconductor-level precision. CoPoS could eventually make it easier to build physically larger packages and possibly improve panel utilization, but the early challenge is matching the fine routing, process control, and yield discipline already developed around wafer-level packaging. CoWoS remains central because AI accelerators are not just large chips; they are tightly packed compute-and-memory systems where latency, signal integrity, power delivery, and manufacturability all collide. If CoPoS matures through the late 2020s and into the early 2030s, it could open useful new design space. For now, TSMC’s roadmap suggests the near-term story is not CoPoS versus CoWoS, but CoPoS plus a still-expanding CoWoS platform. (tomshardware.com)

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